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600 khz dual output synchronous buck pwm controller with linear regulator data s heet adp1876 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their re spective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features wide input range: 2.75 v to 20 v power stage input voltage: 1 v to 20 v output voltage range: 0.6 v up to 90% v in linear dropout (ldo) regulator with a fixed output 1.5 v at 150 ma output current more than 25 a per channel 180 o phase shift between channels for reduced input capacitance 0.85% reference voltage accuracy from ?40c to +85c integrated boost diodes independent channel precision enable overcurrent limit protection externally programmable soft start, slope compensation, and current sense gain thermal overload protection input undervoltage lockout (uvlo) power good with internal pull - up resistor available in 32 - lead, 5 mm 5 mm lfcsp applications consumer applicati ons telecommunications base station and networking industrial and instrumentation typical operation ci rcuit figure 1. general description the adp1876 is a dual output dc - to - dc synchronous buck controller operating at 600 khz fixed frequency with integrated drivers that drive n - channel power mosfets . an additional fixed voltage output, 150 ma linear regulator is available for powering low power loads. t he device operates in current mode for improved transient response and uses valley current sensing for enhanced noise immunity. the two pwm outputs are phase shifted 180 for reducing the input current ripple and the required input capacitance. the adp1876 provides high speed, high peak current drive capability with dead time optimization to enable energy efficient power conversion. ramp1 r ramp1 vin dh1 bst1 sw1 ilim1 fb1 dl1 pgnd1 ramp2 dh2 bst2 sw2 ilim2 fb2 dl2 pgnd2 en1 en2 vdl vcco trk1 1.5v vinldo voutldo nc comp1 comp2 ss1 ss2 agnd r csg1 r1 1 r12 r21 r22 m1 m2 r csg2 m3 l2 l1 v out1 v out2 v in v in m4 r ramp2 pgood1 3v to 5v input pgood2 adp1876 10103-001
adp1876 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical operation circuit ................................................................ 1 gene ral description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 absolute maximum ratings ....................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 14 independent low dropout linear regulator ......................... 14 controller architecture ............................................................. 14 input undervoltage lockout ..................................................... 14 in ternal linear regulator (vcco) .......................................... 14 overvoltage protection .............................................................. 15 power good ................................................................................. 15 short - circuit and current - limit protection .......................... 15 shutdown control ...................................................................... 15 thermal overload protection ................................................... 16 applications information .............................................................. 17 independent low dropout linear regulator ......................... 17 setting the output voltage of the controller ......................... 17 soft start ...................................................................................... 17 setting the current limit .......................................................... 17 accurate current - limit sensing .............................................. 17 setting the slope compensation .............................................. 18 setting the current sense gain ................................................ 18 input capacitor selection .......................................................... 18 input filter .................................................................................. 19 boost capacitor selection ......................................................... 19 inductor selection ...................................................................... 19 output capacitor selection ....................................................... 19 mosfet selection ..................................................................... 20 loop compensation .................................................................. 21 switching noise and overshoot reduction ............................ 22 pcb layout guideline ............................................................... 23 typical applications circuit ..................................................... 23 packaging and ordering information ......................................... 24 outline dimensions ................................................................... 24 ordering guide .......................................................................... 24 revision history 11/11 rev. 0 to rev. a added evaluation board to ordering guide .............................. 24 9/11 revision 0: initial version
data sheet adp1876 rev. a | page 3 of 24 functional block dia gram figure 2 . functional block diagram duplic a te for channe l 2 bst1 pgnd1 + ? + ? + ? + ? + ? + ? fb2 0.6v ov uv pgood1 current sense amplifier dh1 dl1 ilim2 sw1 v ref = 0.6v 6.5 a + + ? error amplifier fb1 comp1 ss1 pwm com p ar a t or dl driver slope com p and ram p gener a t or curren t - limit contro l vcco ramp1 50 a 3.2v g m ov1 + trk1 cs gain driver logic contro l and sta te machine over_lim1 pulse ski p over_lim1 ldo logic en1 en2 vin uvlo oscill a t or 600khz linear regul a t or voutldo vinldo ph1 ph2 ref vcco ov uv 0.6v therma l shutdown agnd 0.6v + ? + ? vcco adp1876 vdl f au l t ov1 logic over_lim1 ov1 en1 en1_sw logic uv1 1k? 0.9v dcm zero cross detect 12k? a v = 3, 6, 12, 24 vcco en1_sw en2_sw nc ? + 10103-002
adp1876 data sheet rev. a | page 4 of 24 specifications all limits at temperature extremes are guaranteed via correlation using standard statistical quality control. v in = 12 v. the specifications are valid for t j = ?40 c to +125 c, unless otherwise specified. typical values are at t a = 25 c. table 1 . parameter symbol test conditions/comments min typ max unit power supply input voltage v in 2.75 20 v undervoltage lockout threshold in uvlo v in rising 2.45 2.6 2.75 v v in falling 2.4 2.5 2.6 undervoltage lockout hysteresis 0.1 v quiescent current i in en1 = en2 = v in = 12 v, v fb = v cco (no switching) 4.5 5.9 ma shutdown current i in_sd en1 = en2 = gnd, v in = 5.5 v or 20 v 100 200 a error amplifier fb input bias current i fb ? 100 +1 +100 na transconductance g m sink or source 1 a 385 550 715 s trk1 input bias current i trk 0 v < v trk1 < 1.5 v ? 100 +1 +100 na current sense amplifier gain a cs gain resistor connected to dlx, r csg = 47 k 5% 2.4 3 3.6 v/v gain resistor connected to dlx, r csg = 22 k 5% 5.2 6 6.9 v/v default setting, r csg = open 10.5 12 13.5 v/v gain resistor connected to dlx, r csg = 100 k 5% 20.5 24 26.5 v/v output characterictistics feedback accuracy voltage v fb t j = ?40 c to +85 c, v fb = 0.6 v ? 0.85% +0.6 +0.85% v t j = ?40 c to +125 c, v fb = 0.6 v ? 1.5% +0.6 +1.5% v line regulation of pwm v fb / v in 0.015 %/v load regulation of pwm v fb / v comp v comp range 0.9 v to 2.2 v 0.3 % oscillator frequency f osc 475 600 690 khz linear regulator vcco vcco output voltage t a = 25c, i vcco = 100 ma 4.8 5.0 5.18 v t j = ?40c to +125c 4.7 5.0 5.3 v vcco load regulation i vcco = 0 ma to 100 ma, 35 mv vcco line regulation v in = 5.5 v to 20 v, i vcco = 20 ma 10 mv vcco short - circuit current 1 vcco < 0.5 v 370 400 ma vin to vcco dropout voltage 2 v dropout i vcco = 100 ma, v in 5 v 0.33 v logic inputs en1, en2 threshold en1/en2 rising 0.57 0.63 0.68 v en1, en2 hysteresis 0.03 v en1, en2 input leakage current i en v in = 2.75 v to 20 v 1 200 na gate drivers (dhx, dlx pins) dhx rise time c dh = 3 n f, v bst ? v sw = 5 v 16 ns dhx fall time c dh = 3 n f, v bst ? v sw = 5 v 14 ns dlx rise time c dl = 3 nf 16 ns dlx fall time c dl = 3 nf 14 ns dhx to dlx dead time external 3 nf capacitor is connected to dhx and dlx 25 ns
data sheet adp1876 rev. a | page 5 of 24 parameter symbol test conditions/comments min typ max unit dhx or dlx driver r on , sourcing current 1 r on_source sourcing 2 a with a 100 ns pulse 2 sourcing 1 a with a 100 ns pulse, v in = 3 v 2.3 dhx or dlx driver r on , tempco tc ron v in = 3 v or 12 v 0.3 %/c dhx or dlx driver r on , sinking current 1 r on_sink sinking 2 a with a 100 ns pulse 1.5 sinking 1 a with a 100 ns pulse, v in = 3 v 2 dhx maximum duty cycle f osc = 600 khz 76 % minimum dhx on time 130 ns minimum dhx off time 340 ns minimum dlx on time 290 ns comp voltage range v comp 0.85 2.3 v thermal shutdown thermal shutdown threshold t tmsd 155 c thermal shutdown hysteresis 20 c overvoltage and power-good thresholds (fbx pins) fbx overvoltage threshold v ov v fb rising 0.67 0.7 0.73 v fbx overvoltage hysteresis 40 mv fbx undervoltage threshold v uv v fb rising 0.51 0.54 0.57 v fbx undervoltage hysteresis 30 mv fb1 to trk1 offset voltage trk1 = 0.3 v to 0.55 v, offset = v fb ? v trk ?120 +50 mv soft start (ssx pins) ssx output current i ss during start-up 4.6 6.5 8.4 a ssx pull-down resistor during a fault condition 1 k power good (pgoodx pins) pgoodx pull-up resistor r pgood internal pull-up resistor to vcco 12.5 k pgoodx delay 12 s overvoltage or undervoltage minimum duration this is the minimum duration required to trip the pgoodx signal 12 s ilim1, ilim2 threshold voltage 1 relative to pgndx ?5 0 +5 mv ilim1, ilim2 output current ilimx = pgndx 40 50 60 a current sense blanking period after dlx goes high, current limit is not sensed during this period 100 ns integrated rectifier (boost diode) resistance at 20 ma forward current 16 independent low dropout linear regulator vinldo voltage range v inldo input range 2.7 5.5 v voutldo voltage v outldo v inldo = 2.7 v to 5.5 v, i outldo = 1 ma to 150 ma 1.47 1.5 1.53 v voutldo maximum load v outldo v inldo = 2.7 v to 5.5 v 150 ma quiescent current i inldo v inldo = 2.7 v to 5.5 v, no load at output 30 60 a line regulation v outldo i outldo = 150 ma, v inldo = 2.7 v to 5.5 v 0.3 % load regulation v outldo v inldo = 2.7 v to 5.5 v, i outldo = 1 ma to 150 ma 0.4 % power supply rejection ratio psrr 1 khz, v indlo = 2.7 v to 5.5 v, 10 ma load 70 db
adp1876 data sheet rev. a | page 6 of 24 parameter symbol test conditions/comments min typ max unit rms output noise n 10 hz to 100 khz, vinldo = 5 v 40 v rms short - circuit current v outldo = gnd 400 ma undervoltage lockout threshold v inldo_uvlo v inldo rising 2.35 2.5 2.65 v undervoltage lockout hysteresis v inldo 0.18 v 1 guaranteed by design. not production tested. 2 connect v in to vcco when v in < 5.5 v.
data sheet adp1876 rev. a | page 7 of 24 absolute maximum ratings table 2 . parameter rating vin, en1/en2, ramp1/ramp2 21 v fb1/fb2, comp1/comp2, ss1/ss2, trk1, vinldo, voutldo, vcco, vdl, pgood1/pgood2 ? 0.3 v to +6 v ilim1/ilim2 ? 0.3 v to +21 v bst1/bst2 to sw1/sw2 ? 0.3 v to +6 v bst1/bst2, dh1/dh2, sw1/sw2 to pgnd1/pgnd2 ? 0.3 v to +28 v dl1/dl2 to pgnd1/pgnd2 ? 0.3 v to vcco + 0.3 v bst1/bst2 to pgnd1/pgnd2, sw1/sw2 to pgnd1/pgnd2 (20 ns transients) 32 v sw1, sw2 to pgnd1, pgnd2 (20 ns transients) 25 v dl1/dl2, sw1/sw2, ilim1/ilim2 to pgnd1/pgnd2 (20 ns negative transients) ? 8 v pgnd1/pgnd2 to agnd ? 0.3 v to +0.3 v pgnd1/pgnd2 to agnd (20 ns transients) ? 8 v to +4 v ja , multilayer pcb (natural convection) 1, 2 32.6c/w operating junction temperature range 3 ? 40c to +125c storage temperature range ? 65c to +150c maximum soldering lead temperature 260c 1 measured with exposed pad attached to the printed circuit board (pcb). 2 junction - to - ambient thermal resistance ( ja ) of the package was calculated or simulated on a multilayer pcb. 3 the junction temperature, t j , of the device is dependent on the ambient temperature, t a , the power dissipation of the device, p d , and the junction to ambient thermal resistance of the package, ja . maximum jun ction temperature is calculated from the ambient temperature and power dissipation using the formula, t j = t a + p d ja . absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenced to gnd. esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y .
adp1876 data sheet rev. a | page 8 of 24 pin configuration an d function descripti ons figure 3 . pin configuration table 3 . pin function descriptions pin no. mnemonic description 1 en1 enable input for channel 1. drive en1 high to turn on the channel 1 controller, and drive it low to turn it off. tie en1 to vin for automatic startup. for a precision uvlo, put an appropriately sized resistor divider from vin to agnd and tie the midpoint t o this pin. 2 vin connect to main power supply. bypass with a 1 f or larger ceramic capacitor connected as close to this pin as possible and pgndx. 3 vinldo input for independent linear dropout (ldo) regulator. 4 voutldo output for independent ldo regulator. 5 vcco output of the internal ldo. the internal circuitry and gate drivers are powered from vcco. bypass vcco to agnd with a 1 f or larger ceramic capacitor. the vcco output is always active, even during fault conditions, and it cannot be turn ed off even when en1 or en2 is low. for operation at vin below 5 v, vin can be jumped to vcco. do not use the vcco to power any other auxiliary system load. 6 vdl power supply for the low - side driver. bypass vdl to pgndx with a 1 f ceramic capacitor. connect vcco to vdl. 7 agnd analog ground. 8 nc no connect. do not connect to this pin. 9 en2 enable input for channel 2. drive en2 high to turn on the channel 2 controller, and drive it low to turn off. tie en2 to vin for automatic startup. for a precision uvlo, put an appropriately sized resistor divider from vin to agnd and tie the midpoint to t his pin. 10 fb2 output voltage feedback for channel 2. 11 comp2 compensation node for channel 2. output of the channel 2 error amplifier. connect a series resistor/capacitor network from comp2 to agnd to compensate the regulation control loop. 12 ra mp2 programmable current setting for slope compensation of channel 2. connect a resistor from ramp2 to vin. the voltage at ramp2 is 0.2 v during operation. this pin is high impedance when the channel is disabled. 13 ss2 soft start input for channel 2. connect a capacitor from ss2 to agnd to set the soft start period. this node is internally pulled up to 3.2 v through a 6.5 a current source. 14 pgood2 open - drain power - good indicator logic output at pgood2. an internal 1 2 k resistor is connected between pgood2 and vcco. pgood2 is pulled to ground when the channel 2 output is outside the regulation window. an external pull - up resistor is not required. 15 ilim2 current - limit sense comparator inverting input for channel 2 . connect a resistor between ilim2 and sw2 to set the current - limit offset. for accurate current - limit sensing, connect ilim2 to a current sense resistor at the source of the low - side mosfet. 16 bst2 boot strapped upper rail of high - side internal driver for channel 2. connect a 0.1 f to 0.22 f multilayer ceramic capacitor (mlcc) between bst2 and sw2. there is an internal boost rectifier connected between vdl and bst2. 24 sw1 23 dh1 22 pgnd1 21 dl1 20 dl2 19 pgnd2 18 dh2 17 sw2 1 2 3 4 5 6 7 8 en1 vin vinldo voutldo vcco vdl agnd nc 9 10 1 1 12 13 14 15 16 en2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 32 31 30 29 28 27 26 25 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 adp1876 t op view (not to scale) notes 1. nc = no connec t . do not connect t o this pin. 2. connect the bot t om exposed p ad of the lfcs p p ackage t o system agnd plane. 10103-003
data sheet adp1876 rev. a | page 9 of 24 pin no. mnemonic description 17 sw2 switch node for channel 2. connect to the source of the high - side n - channel mosfet and the drain of the low - side n - channel mosfet of channel 2. 18 dh2 high - side switch gate driver output for channel 2. 19 pgnd2 power ground for channel 2. ground for internal channel 2 driver. differential current is sensed between sw2 and pgnd2. directly shorting pgnd2 to pgnd1 is not recommended. 20 dl2 low - side synchronous rectifier gate driver output for channel 2. to set th e gain of the current sense amplifier, connect a resistor between dl2 and pgnd2. 21 dl1 low - side synchronous rectifier gate driver output for channel 1. to set the gain of the current sense amplifier, connect a resistor between dl1 and pgnd1. 22 pgnd1 power ground for channel 1. ground for internal channel 1 driver. differential current is sensed between sw1 and pgnd1. directly shorting pgnd2 to pgnd1 is not recommended. 23 dh1 high - side switch gate driver output for channel 1. 24 sw1 power switch no de for channel 1. connect sw1 to the source of the high - side n - channel mosfet and the drain of the low - side n - channel mosfet of channel 1. 25 bst1 boot strapped upper rail of high - side internal driver for channel 1 . connect a 0.1 f to 0.22 f multilayer ceramic capacitor (mlcc) between bst 1 and sw 1 . there is an internal boost diode or rectifier connected between vdl and bst1. 26 ilim1 current - limit sense comparator inverting input for channel 1. connect a resistor between ilim1 and sw1 to set the current - limit offset. for accurate current - limit sensing, connect ilim1 to a current sense resistor at the source of the low - side mosfet. 27 pgood1 open -d rain power - good indicator logic output. pgood1 includes an internal 12 k resistor connected between pgood1 and vcco. pgood1 is pulled to ground when the channel 1 output is outside the regulation window. an external pull - up resistor is not required. 28 ss1 soft start input for channel 1. connect a capacitor from ss1 to agnd to set the soft start period. this node is internally pulled up to 3.2 v through a 6.5 a current source. 29 ramp1 programmable current setting for channel 1 slope compensation. connect a resistor from ramp1 to vin. the voltage at ramp1 is 0.2 v during operation. this pin is high impedance when the channel is disabled. 30 comp1 compensation node for channel 1. output of channel 1 error amplifier. connect a series resistor/capacitor network from comp1 to agnd to compensate the regulation control loop. 31 fb1 output voltage feedback for channel 1. 32 trk1 tracking input for channel 1.
adp1876 data sheet rev. a | page 10 of 24 typical performance characteristics test conditions are at t a = 25c and v in = 12 v, unless otherwise specified. figure 4 . efficiency plot of figure 33 figure 5 . vcco dropout figure 6 . vcco line regulation figure 7 . vcco vs. v in figure 8 . step load transient of figure 33 figure 9 . soft start into precharged output 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 14 efficienc y (%) load (a) v i n = 12 v v out = 1 .8v v out = 5v 10103-004 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 2.5 3.0 3.5 4.0 4.5 5.0 vcco (v) v in (v) 50m a load 100m a load 10103-005 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5 7 9 1 1 13 15 17 vcco (v) v in (v) no load on ldo 100m a load on ldo 10103-006 0 1 2 3 4 5 6 0 1 2 3 4 5 6 vcco (v) v in (v) 10103-007 10103-008 ch1 5.00a ? ch3 20.0mv m100s a ch1 9.00a 1 3 vout1 = 5v output response output step load = 5a to 10a 2 ch3 1v ch2 5v ch1 5v ch4 1 a ? m1ms a ch1 2.4v v in = 12v v out = 1.8v output precharged t o 1v dh1 dl1 vout1 il1 1 3 4 10103-009
data sheet adp1876 rev. a | page 11 of 24 figure 10 . enable startup function figure 11 . thermal shutdown waveform figure 12 . change in f sw vs. v in figure 13 . f sw vs. temperature figure 14 . typical dhx minimum on time and off time figure 15 . dhx minimum on time and off time over temperature ch3 1v ch2 2v ch1 10v ch4 1v m10ms a ch2 1.52v c ss = 100nf v out (ch3) ss (ch4) en sw 1 2 3 4 10103-010 10103-011 ch1 10.0v b w ch3 2.00v b w m10.0ms a ch4 800mv 4 2 1 ch2 2.00v b w ch4 1.00v b w sw1 vout1 (preloaded) voutldo vcco ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 change in f sw (%) v in (v) 600 kh z reference at v in = 2.75v 10103-012 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?40 ?15 10 35 60 85 1 10 135 change in f sw (%) temper a ture (c) v in = 12 v ; referenced a t 25c 10103-013 50 100 150 200 250 300 350 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 time (ns) v in (v) dhx minimum off time dhx minimum on time 10103-014 ?4 ?3 ?2 ?1 0 1 2 3 4 ?40 ?15 10 35 60 85 1 10 135 change in minimum on/off time (%) temper a ture ( c) dhx minimum on time dhx minimum off time 10103-015
adp1876 data sheet rev. a | page 12 of 24 figure 16 . dead time vs. temperature figure 17 . dead time vs. v in figure 18 . g m of error amplifier vs. temperature figure 19 . driver resistance vs. temperature figure 20 . voutldo line regulation figure 21 . voutldo load regulation 25 35 34 33 32 31 30 29 28 27 26 ?40 ?20 0 20 40 60 80 100 120 140 dead time (ns) temper a ture (c) v in = 12v output is loaded hs fet = bsc080n03ls ls fet = bsc030n03ls dead time between swx f alling edge and dlx rising edge, including diode recove r y time 10103-016 25 45 43 41 39 37 35 33 31 29 27 0 20 15 10 5 dead time (ns) v in (v) t a = 25c output is loaded hs fet = bsc080n03ls ls fet = bsc030n03ls dead time between swx f alling edge and dlx rising edge, including diode recove r y time 10103-017 400 420 440 460 480 500 520 540 560 580 600 ?40 ?15 10 35 60 85 1 10 135 g m (s) temper a ture (c) v in = 2.75v t o 20v 10103-018 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?40 ?15 10 35 60 85 1 10 135 driver resis t ance (?) temper a ture (c) v in = 2.75 v , sourcing v in = 12 v , sourcing v in = 2.75 v , sinking v in = 12 v , sinking 10103-019 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 3.0 3.5 4.0 4.5 5.0 5.5 6.0 line regulation (%) vinldo (v) 10103-020 ?0.20 ?0.18 ?0.16 ?0.14 ?0.12 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.025 0.050 0.075 0.100 0.125 0.150 0.175 0.200 load regul a tion (%) voutldo load (a) vinldo = 3v vinldo = 5v 10103-021
data sheet adp1876 rev. a | page 13 of 24 figure 22 . voutldo noise spectral density figure 23 . voutldo step load transient 0 5 10 15 20 25 30 35 10 100 1m 10m 100m 1 rms noise (v) voutldo load (a) 10103-022 10103-023 ch1 100ma ? b w m10.0s a ch1 118ma 2 1 ch2 50.0mv b w step load 1ma to 200ma cinldo = 1f; coutldo = 4.7f output transient
adp1876 data sheet rev. a | page 14 of 24 theory of operation the adp1876 is a dual output dc - to - dc synchronous buck controller with integrated drivers that drive n - channel power mosfets . the device operates in current mode for improved transient response and uses valley current sensing for enhanced noise immunity . the two outputs are phase shifted 180. this reduces the input current ripple and the required input capacitance. the integrated boost diodes in the adp1876 reduce the overall system cost and component count. the adp1876 operates at a fixed frequency of 600 khz and includes programmable soft start, current limit, and power good. indepen dent low dropout lin ear regulator in addition to the dual channel step - down controller, a stand - alone li near dropout (ldo) voltage regulator with a fixed output of 1.5 v is built into the adp1876 and operates independently from the controllers. the output of the ldo delivers up to 150 ma to the load. see the applications information section for more information. controller architect ure the adp1876 is based on a fixed frequency, current mode pwm control architecture. the inductor current is sensed by the voltage drop measured across the external low - s ide mosfet r dson during the off period of the switching cycle (valley inductor current). the current sense signal is further processed by the current sense amplifier. the output of the current sense amplifier is held, and the emulated current ramp is multi plexed and fed into the pwm comparator (see figure 24 ). the valley current information is captured at the end of the off period, and the emulated cur rent ramp is applied at that point when the next on cycle begins. an error amplifier integrates the error between the feedback voltage and the generated error voltage from the comp pin (see the from error amp in fi gure 24 ). figure 24 . simplified control architecture as shown in figure 24 , the emulated current ramp is generated inside the ic but offers programmability through the rampx pin (see figure 1 for the typical operation circuit). selecting an appropriate value resistor from v in to the rampx pin programs a desired slope compensation value and, at the same time, provides a feedforward feature. the benefits realized by deploying this type of control scheme are as follows: ? the turn - on current spike does not corrupt the current ramp. ? the current signal is stable because the current signal is sampled at the end of the turn - off period, which gives time for the switch node ringing to settle. the normal benefits of using current mode control scheme still apply, such as simplicity of loop compensation. control log ic enforces antishoot through operation to limit cross conduct ion of the internal drivers and external mosfets. sy nchronous rectifier and dead time the synchronous rectifier (low - side mosfet) improves efficiency by replacing the schottky diode that is normally used in an asynchronous buck regulator. in the adp1876 , the ant ishoot through circuit monitors the sw and dl nodes and adjusts the low - side and high - side drivers to ensure break - before - make switching to prevent cross conduction or shoot through between the high - side and low - side mosfets. this break - before - make switchi ng is known as the dead time, which is not fixed and depends on how fast the mosfets are turned on and off. in a typical application circuit that uses medium sized mosfets with input capacitance of approximately 3 nf, the typical dead time is approximately 30 ns. when small and fast mosfets are used, the dead time can be as low as 13 ns. input undervoltage l ockout when the bias input voltage, v in , is less than the undervoltage lockout (uvlo) threshold, the switch drivers stay inactive. when v in exceeds the uvlo threshold, the switchers begin switching. internal linear regu lator (vcco) the internal linear regulator is low dropout, meaning it can regulate its output voltage, vcco. vcco powers the internal control circuitry and provides power for the gate drive rs. it is guar - anteed to have more than 200 ma of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold mosfets. vcco is always active and cannot be shut down by the en1/en2 pins. bypass vcco to agn d with a 1 f or greater capacitor. because the ldo supplies the gate drive current, the output of vcco is subject to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. ff osc q q s r a cs v cs v in v in a r r ram p i ram p c r from error am p t o drivers from low side mosfet 10103-024
data sheet adp1876 rev. a | page 15 of 24 the ldo has been optimize d to handle these transients without overload faults. due to the gate drive loading, using the vcco output for other external auxiliary system loads is not recom - mended. the ldo includes a current limit well above the expected maximum gate drive load. this current limit also includes a short - circuit fold back to further limit the vcco current in the event of a short - circuit fault. the vdl pin provides power to the low - side driver. connect vdl to vcco. bypass vdl to pgnd with a 1 f (minimum) ceramic capacit or, which must be placed close to the vdl pin. for an input voltage of less than 5.5 v, it is recommended to bypass the ldo by connecting vin to vcco, as shown in figure 25 , thus eliminating the dropout voltage. however, for example, if the input range is 4 v to 7 v, the ldo cannot be bypassed by shorting vin to vcco because the 7 v input has exceeded the maximum voltage rating of the vcco pin. in this case, use the ldo to drive the internal drivers noting that there is a dropout when v in is less than 5 v. figure 25 . configuration for v in < 5.5 v overvoltage protecti on the adp1876 operates at a 600 khz fixed frequency pwm. when the output is shorted to a voltage higher than the regu - lation voltage, t he duty cycle of the controller modulates to ke ep the output stable at the preset regulation voltage by sinking current through the lo w - side n - chann el mosfet during th e off cycle. power good the pgoodx pin is an open - drain nmos with an internal 12 k? pull - up resistor connected between pgoodx and vcco. pgoodx is internally pulled up to vcco during normal operation and is active low whe n tripped. when the feedback voltage, v fb , rises above the overvoltage threshold or drops below the undervoltage threshold, the pgoodx output is pulled to ground after a delay of 12 s. the overvoltage or under - voltage condition must exist for more than 12 s for pgoodx to become active. the pgoodx output also becomes active if a thermal overload condition is detected. short - circuit and current - limit protection when the output is shorted or the output current exceeds the current limit set by the current - l imit setting resistor (between ilimx and swx) for eight consecutive cycles, the adp1876 shuts off both the high - side and low - side drivers and restarts the soft start sequence every 10 ms, which is known as hicc up mode. the ss node discharges to zero through an internal 1 k? resistor during an overcurrent or short - circuit event. figure 26 shows that the adp1876 (a 20 a application circuit) is entering current - limit hiccup mode when the output is shorted. figure 26 . current - limit hiccup mode, 20 a circuit shutdown control the en1 and en2 pi ns enable or disable channel 1 and channel 2, respectively, of the adp1876 . the precision enable threshold for en1 or en2 is typically 0.63 v. when the en1 or en2 voltage rises above 0.63 v, the adp1876 is enabled and starts normal operation after the soft start period. when the voltage at enx drops below 0.57 v, the switchers and the internal circuits in the adp1876 are turned off. note that en1/en2 cannot shut down the voutldo or vcco, which are always active. for the purpose of start - up power sequencing, the startup of the adp1876 can be programmed by connecting an appropriate resistor divider from the master power supply to the en1 or en2 pin, as shown in figure 27 . for instance, if the desired start - up volt age from the master power supply is 10 v, r1 and r2 can be set to 156 k? and 10 k?, respectively. figure 27 . optional power - up sequencing circuit v in = 2.75v t o 5.5v adp1876 vin vcco 10103-025 ch3 500mv ch1 10v ch4 10 a ? m2ms a ch1 1 1.2v sw1 ss1 induc t or current 1 3 4 10103-026 adp1876 fb1 or fb2 en1 or en2 r t op r bot v out1 r1 r2 master supp l y vo lt age 10103-027
adp1876 data sheet rev. a | page 16 of 24 thermal overload pro tection the adp18 76 has an internal temperature sensor that senses the junction temperature of the chip. when the junction tem - perature of the adp1876 reaches approximately 155c, the adp1876 enters thermal shutdown, where the converter, vcco, and voutldo are turned off and ssx discharges toward zero through an internal 1 k? resistor. when the junction temperature drops below 135c, the a dp1876 resumes normal operation after the soft start sequence.
data sheet adp1876 rev. a | page 17 of 24 applications informa tion independent low drop out linear regulator the input voltage range to vinldo of the independent ldo regulator is 2.7 v to 5.5 v, and the output is fixed at 1.5 v with a 150 ma maximum load current. the internal short - circuit current limit is set to about 430 ma. apply power to the vin pin to keep the ldo operating within specification. the ldo is enabled when v inldo exceeds the inp ut undervoltage lockout (uvlo) t hreshold. safety features include short - circuit protection and thermal overload shutdown. setting the output v oltage of the controller the output voltage is set using a resistive voltage divider from the output to fbx. the v oltage divider divides down the output voltage to the 0.6 v fbx regulation voltage to set the regulation output voltage. the output voltage can be set to as low as 0.6 v and as high as 90% of the power input voltage. the maximum input bias current into fbx is 100 na. for a 0.15% degradation in regulation voltage, and with 100 na bias current, the low - side resistor, r bot , must be less than 9 k?, which results in 67 a of divider current. for r bot , use a 1 k to 20 k resistor. a larger value resistor can be used but results in a reduction in output voltage accuracy due to the input bias current at the fbx pin, whereas lower values cause increased quiescent current consumption. choose r top to set the output voltage by using the following equation: ? ? ? ? ? ? ? ? ? = fb fb out bot top v v v r r where: r top is the high - side voltage divider resistance. r bot is the low - side voltage divider resistance. v out is the regulated output voltage. v fb is the feedback regulation threshold, 0.6 v. the minimum output voltage is dependent on f sw and minimum dhx on time. the maximum output voltage is dependent on f sw , the minimum dhx off time, the ir drop across the high - side n - channel mosfet, and the dcr of the inductor. soft start the soft start period is set by an external capacitor between ss1 or ss2 and agnd. the soft start function limits the input inrush current and prevents output overshoot. when en1/en2 is enabled, a current source of 6.5 a starts charging the capacitor, and the regulation volt age is reached when the voltage at ss1/ss2 reaches 0.6 v. the soft start period is approximated by the following equation: ss ss c t a 5 . 6 v 6 . 0 = the ssx pin reaches a final voltage of 3.2 v. if the output voltage is precharged prior to turn on, the adp1876 prevents reverse inductor current, which discharges the output capacitor. when the voltage at ssx exceeds the regulation voltage (typically at 0.6 v), the reverse current is enabled to allow the output volt age regulation to be independent of load current. when a controller is disabled, for instance, en1/en2 is pulled low or experiences an overcurrent limit condition, the soft start capacitor is discharged through an internal 1 k? pull - down resistor. setting the current limit the current - limit comparator measures the voltage across the low - side mosfet to determine the load current. the current limit is set by an external current - limit resistor, r ilim, between ilimx and swx. the current sense pin, ilimx, sour ces nominally 50 a to this external resistor. this creates an offset voltage of r ilim multiplied by 50 a. when the drop across the low - side mosfet r dson is equal to or greater than this offset voltage, the adp1876 flags a current - limit event. because the ilimx current and the mosfet r dson vary over process and temperature, set the minimum current limit to ensure that the system can handle the maximum desired load current. to do this, use the peak current in the inductor, which is the desired output current - limit level, plus ? of the ripple current, the maximum r dson of the mosfet at its highest expected temperature, and the minimum ilim current. keep in mind that the temperature coefficient of the mosfet r dson is typically 0.4%/c. a 40 _ max dson lpk ilim r i r = where: i lpk is the peak inductor current. accurate current - limit sensing r dson of the mosfet can vary by more than 50% over the temperature range. accurate current - limit sensing is achieved by adding a curre nt sense resistor from the source of the low - side mosfet to pgndx. make sure that the power rating of the current sense resistor is adequate for the application . apply the previous equation and calculate r ilim by replacing r dson_max with r sense . see figure 28 for the implementation of this accurate current - limit sensing scheme.
adp1876 data sheet rev. a | page 18 of 24 figure 28 . accurate current - limit sensing setting the slope compensati on in a current mode control topology, slope compensation is needed to prevent subharmonic oscillations in the inductor current and to maintain a stable output. the external slope compensation is implemented by summing the amplified sen se signal and a scaled voltage at the rampx pin. to implement the slope compensation, connect a resistor between rampx and the input voltage. the resistor, r ramp , is calculated by max dson cs ramp r a l r _ 10 10 6 . 3 = where: 3.6 10 10 is an internal parameter. l is the inductance of the inductor. r dson_max is the the low - side mosfet maximum on resistance. a cs is the gain, either 3 v/v, 6 v/v, 12 v/v, or 24 v/v, of the current sense amplifier (see the setting the current se nse gain section for more details). keep in mind that r dson is temperature dependent and can vary as much as 0.4%/ o c. choose r dson at the maximum operating temperature. the voltage at ramp x is fixed at 0.2 v, and the current going into rampx should be between 6 a and 200 a. ensure that the following condition is satisfied: a 200 v 2 . 0 a 6 ? ramp in r v for instance, with an input voltage of 12 v, r ramp should not exceed 1.9 m?. if the calculated r ramp produces less than 6 a , select an r ramp value that produces between 6 a and 20 a. figure 29 illu strates the connection of the slope compensa tion resistor, r r amp , and the current sense gain resistor, r csg . figure 29 . slope compensation and cs gain connection setting the current sense gain the voltage drop across the external low - side mosfet is sensed by a current sense amplifier by multiplying the peak inductor current and the r dson of the mosfet. the result is amplified by a gain factor of either 3 v/v, 6 v/v, 12 v/v, or 24 v/v, which is programmable by an external resistor, r csg , connected to the dlx pin. this gain is sensed during power - up only and not during normal operation. the amplified voltage is summed with the slope compensation ramp voltage and fed into the pwm controller for a stable regulation voltage. the voltage range of the internal node, v cs , is between 0.4 v and 2.2 v. select the current sense gain such that the internal minimum amplified voltage (v csmin ) is above 0.4 v and the maximum amplified voltage (v csmax ) is 2.1 v. note that v csmin or v csmax is not the same as v comp , which has a range of 0.85 v to 2.3 v. make sure that the maximum v comp (v compmax ) does not exceed 2.2 v to account for temperature and device to device variations. the following are equations for v csmin , v csmax , and v compmax : cs min dson lpp csmin a r i v ? = _ 2 1 v 75 . 0 cs max dson lpp loadmax csmax a r i i v + + = _ ) 2 1 ( v 75 . 0 ( ) csmax ramp on in compmax v r t v v + ? = pf 25 v 2 . 0 whe re: v csmin is the minimum amplified voltage of the internal current sense amplifier at zero output current. v csmax is the maximum amplified voltage of the internal current sense amplifier at maximum output current. r dson_min is the the low - side mosfet m inimum on resistance. i lpp is the peak - to - peak ripple current in the inductor. i loadmax is the maximum output dc load current. v compmax is the maximum voltage at the comp pin. a cs is the current sense gain of either 3 v / v, 6 v / v, 12 v / v, o r 24 v/v set by the gain resistor between dlx and pgndx. 25 pf is an internal parameter. t on is on time for the high - side driver (dh). input capacitor sele ction the input current to a buck convert er is a pulse waveform. it is zero when the high - side switch is off and approximately equal to the load current when it is on. the input capacitor carries the input ripple current, allowing the input power source to supply only the direct current. the inpu t capacitor needs a sufficient ripple current rating to handle the input ripple, as well as an equivalent series resistance (esr) that is low enough to mitigate input voltage ripple. for the usual current ranges for these con - verters, it is good practice t o use two parallel capacitors placed close to the drains of the high - side switch mosfets (one bulk capacitor of sufficiently high current rating and a 10 f ceramic decoupling capacitor, typically). v in adp1876 dhx swx ilimx dlx r ilim r sense 10103-028 pgndx v in adp1876 dhx swx ilimx dlx r ilim r csg ramp r ramp 10103-029 pgndx
data sheet adp1876 rev. a | page 19 of 24 select an input bulk capacitor based on its ripple curr ent rating. first, determine the duty cycle of the output. in out v v d = the input capacitor rms ripple current is given by ) 1 ( d d i i o rms ? = where: i o is the output current. d is the duty cycle. the minimum input capacitance required for a particular load is sw esr o pp o min in f r d i v d d i c ) ( ) 1 ( , ? ? = where: v pp is the desired input ripple voltage. r esr is the equivalent series resistance of the capacitor. if an mlcc capacitor is used, the esr is near 0, then the equation is simplified to sw pp o min in f v d d i c ? = ) 1 ( , the capacitance of mlcc is voltage dependent. the actual capacitance of the selected capacitor must be derated according to the manufacturers specification . in addition, add more bulk capacitance, such as by using electrolytic or polymer capacitors, as necessary for large step load transients. make sure the current ripple rating of the bulk capacitor exceeds the maximum input current ripple of a particular design. input filter normally a 0.1 f (or greater value) bypass capacitor from the in put pin (vin) to agnd is sufficient for filtering any unwanted switching noise. however, depending on the printed circuit board (pcb) layout, some switching noise can enter the adp1876 internal circuitry; therefore, it is r ecommended to have a low - pass filter at the vin pin. connecting a resistor, between 2 ? and 5 ?, in series with vin and a 1 f ceramic capacitor between vin and agnd creates a low - pass filter that effe ctively filters out any unwanted glitches caused by the switching regulator. note that the input current can be larger than 100 ma when driving large mosfets. a 100 ma current across a 5 ? resistor creates a 0.5 v drop, which is the same voltage drop in vcco. in this case, a lower resistor value is desirable. figure 30 . input filter configuration boost capacitor sele ction to lower system component count and cost, the adp1876 has an integrated rectifier (equivalent to the boost diode) betw een vcco and bstx. choose a boost ceramic capacitor with a value between 0.1 f and 0.22 f; this capacitor provides the current for the high - side driver during switching. inductor selection the ou tput lc filter smoothes the switched voltage at swx . for most applications, choose an inductor value such that the inductor ripple current is between 20% and 40% of the maximum dc output load current. generally, a larger inductor current ripple generates more power loss in the inductor and larger voltage ripples at the output. check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak inductor current of a particular design. choose the inductor value by using the following equation: in out l sw out in v v i f v v l ? ? = where : l is the inductor value. f sw is the switching frequency. v out is the output voltage. v in is the input voltage. ? i l is the inductor ripple current. output capacitor sel ection choose the output bulk capacitor to set the desired output voltage ripple. the impedance of the output capacitor at the switching frequen cy multiplied by the ripple current gives the output voltage ripple. the impedance comprises the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resis - tance (esr), and the equivalent series inductance (esl). the output voltage ripple can be approximated by ? ? ? ? ? ? ? ? + + ? ? ? esl sw out sw esr l out l f c f r i v 4 8 1 where: ? v out is the output ripple voltage. ? i l is the inductor ripple current. r esr is the equivalent series resistance o f the output capacitor (or the parallel combination of esr of all output capacitors). l esl is the equivalent series inductance of the output capacitor (or the parallel combination of esl of all capacitors). solving c out in the previous equation yields esl sw l esr l out sw l out l f i r i v f i c ? ? ? ? ? ? ? 4 1 8 adp1876 vin v in agnd t 2 1f 10103-030
adp1876 data sheet rev. a | page 20 of 24 usually, the impedance is dominated by esr, such as in electrolytic or polymer capacitors, at the switching frequency, as stated in the maximum esr rating on the capacitor data sheet; therefore, output ripple reduces to esr l out r i v ? ? ? electrolytic capacitors also have significant esl, on the order of 5 nh to 20 nh, depending on type, size, and geometry. pcb traces contribute some esr and esl, as well. however, using the maximum esr rating from the capacitor data sheet often prov ides enough margin such that measuring the esl is not usually required. in the case of output capacitors where the impedance of the esr and esl are small at the switching frequency, for instance, where the output capacitor is a bank of parallel mlcc capac itors, the capacitive impedance dominates and the output capacitance equation reduces to sw out l out f v i c ? ? ? 8 ensure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. for example, during a load step transient on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. this initial output voltage deviation results in a voltage droop or undershoot . the output capacitance (assuming 0 ? esr) that is required to satisfy the voltage droop requirement can be approximated by sw droop step out f v i c ? ? ? where: ? i step is the step load. ? v droop is the voltage droop at the output. when a load is suddenly removed from the output, the energy stored in the inductor rushes into the capacitor, causing the output to overshoot. the output capacitance required to satisfy the output overshoot requirement can be approximated by 2 2 2 ) ( out overshoot out step out v v v l i c ? ? + ? ? where: ? v overshoot is the ov ershoot voltage during the step load. select the largest output capacitance given by any of the previous three equations. mosfet selection the choice of mosfet directly affects the dc - to - dc converter performance. a mosfet with low on resistance reduces i 2 r l osses, an d a low gate charge r educes transition losses. a mosfet that ha s low thermal resistance en sures that the power dissipated in the mosfet does not result in excessive mosfet die tem - perature. the high - side mosfet carries the load current during on time and usually carries most of the transition losses of the converter. typica lly, the lower the on resistance of the mosfet, the higher the gate charge, and vice versa. therefore, it is important to choose a high - side mosfet that balances the two losses . the conduction loss of the high - side mosfet is determined by the equation ? ? ? ? ? ? ? ? ? in out dson load c v v r i p 2 ) ( where: r dson is the mosfet on resistance. the gate charging loss is approximated by the equation p g ? v pv q g f sw where v pv is the ga te driver supply voltage. q g is the mosfet total gate charge. note that the gate charging power loss is not dissipated in the mosfet but rather in the adp1876 internal drivers. this power loss must be considered when calculating the overall power efficiency. the high - side mosfet transition loss is approximated by the equation 2 ) ( sw f r load in t f t t i v p + ? where: p t is the high - side mosfet switching loss power. t r is t he rise time in charging the high - side mosfet. t f is the fall time in discharging the high - side mosfet. t r and t f can be estimated by the following equations: rise driver gsw r i q t _ ? fall driver gsw f i q t _ ? where: q gsw is the gate charge of the mosfet during switching and is given in the mosfet data sheet. i driver_rise and i driver_fall are the driver current output by the adp1876 internal gate drivers. if q gsw is not given in the data sheet, it can be approximate d by 2 gs gd gsw q q q + ? where q gd and q gs are the gate - to - drain and gate - to - source charges given in the mosfet data sheet. i driver_rise and i dri ver _fall can be estimated by gate source on sp dd rise driver r r v v i + ? ? _ _
data sheet adp1876 rev. a | page 21 of 24 gate sink on sp fall driver r r v i + ? _ _ where: v dd is the input supply voltage to the driver and is between 2.75 v and 5 v, depending on the input voltage. v sp is the switching point where the mosfet fully conducts; this voltage can be estimated by inspecting the gate charge graph given in the mosfet data sheet. r on_source is the on resistance of the adp1876 internal driver (listed in table 1 ), when charging the mosfet. r on_sink is the on resistance of the adp1876 internal driver (listed in table 1 ), when discharging the mosfet. r gate is the on gate resistance of mosfet listed in the mosfet data sheet. if an external gate resistor is added, add this external resistance to r gate . the to tal power dissipation of the high - side mosfet is the sum of conduction and transition losses: t c hs p p p + ? the synchronous rectifier, or low - side mosfet, carries the inductor current when the high - side mosfet is off. the low - side mosfet transitio n loss is small and can be neglected in the calculation. for high input voltage and low output voltage, the low - side mosfet carries the current most of the time. therefore, to achieve high efficiency, it is critical to optimize the low - side mosfet for low on resistance. in cases where the power loss exceeds the mosfet rating or lower resistance is required than is available in a single mosfet, connect multiple low - side mosfets in parallel. the equation for low - side mosfet conduction power loss is ? ? ? ? ? ? ? ? in out dson load cls v v r i p 1 ) ( 2 there is an additional power loss during the time known as dead time between the turn off of the high - side switch and the turn on of the low - side switch when the body diode of the low - side mosfet conducts the output current. the power loss in the body diode is given by p bodydiode = v f t d f sw i o where: v f is the forward voltage drop of the body diode, typically 0.7 v. t d is the dead time in the adp1876 , typically 30 ns when drivi ng some medium - size mosfets with input capacitance, c iss , of approximately 3 nf. the dead time is not fixed. its effective value varies with gate drive resistance and c iss thereby increasing p bodydiode in high load current designs and low voltage designs. therefor e, the power loss in the low - side mosfet becomes p ls = p cls + p bodydiode note that mosfet r dson increases as temperature increases with a typical temperature coefficient of 0.4%/ o c. the mosfet junction temperature rise over the ambient temperature is t j = t a + ja p d where: ja is the thermal resistance of the mosfet package. t a is the ambient temperature. p d is the total power dissipated in the mosfet. loop compensation as with most current mode step - down controllers, a trans - conductance error amplif ier is used to stabilize the external voltage loop. compensating the adp1876 is fairly easy; an rc compensator is needed between comp and agnd. figure 31 shows the configuration of the compensation components: r comp , c comp , and c c2 . because c c2 is very small compared to c comp , to simplify calculation, c c2 is ignored for the stability compensation analysis. figure 31 . compensation components the open - loop gain transfer function at angular frequency, s, is given by ) ( ) ( ) ( s z s z v v g g s h filter comp out ref cs m = (1) where: g m is the transconductance of the error amplifer, 500 s g cs is the tranconductance of the current sense amplifier. z comp is the impedance of the compensation network. z f ilter is the impedance of the output filter. v ref = 0.6 v g cs with units of a/v is given by min dson cs cs r a g _ 1 = (2) where: a cs is the current sense gain of either 3 v/v , 6 v / v, 12 v / v, o r 24 v/v set by the gain resistor between dlx and pgndx. r dson_min is the the low - side mosfet minimum on resistance. if a sense resistor, r s , is added in series with the low - side fet, then g cs becomes ) ( 1 _ s min dson cs cs r r a g + = adp1876 fbx c com p g m 0.6v compx agnd r com p c c2 10103-031
adp1876 data sheet rev. a | page 22 of 24 because the zero produced by the esr of the output capacitor is not needed to stabilize the control loop, assuming esr is small, the esr is ignored for analysis. then, z filter is given by out filter sc z 1 = (3) bec ause c c2 is small relative to c comp , z comp can be simplified to comp comp comp comp comp comp sc c sr sc r z + = + = 1 1 (4) at the crossover frequency, the open - loop transfer function is unity of 0 db, h (f cross ) = 1 . combining equation 1 and equa - tion 3, z comp at the crossover frequency can be written as ) )( 2 ( ) ( ref out out cs m cross cross comp v v c g g f f z = (5) the zero produced by r comp and c comp is comp comp zero c r f = 2 1 (6) at the crossover frequency, equation 4 can be shown as cross zero cross comp cross comp f f f r f z 2 ) ( 2 + = (7) combining equation 5 and equation 7 and solving for r comp gives ) ( ) 2 ( ref out out cs m cross zero cross cross comp v v c g g f f f f r + = (8) choose the cross over and zero frequencies as follows: 12 sw cross f f = (9) 48 4 sw cross zero f f f = = (10) substituting equation 2, equation 9, and equation 10 into equation 8 yields ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ref out out m cross dson cs comp v v c g f r a r 2 97 . 0 (11) where: g m is the transconductance of the error amplifer, 500 s. a cs is the current sense gain of 3 v / v, 6 v / v, 12 v / v, o r 24 v / v. r dson is the on resistance of the low - side mosfet. v ref = 0.6 v. and combining equation 6 and equation 10 yields cross comp comp f r c = 2 (12) note that the previous simplified compensation equations for r comp and c comp yield reasonable results in f cross and phase margin assuming that the compensation ramp current is ideal. varying the ramp current, or deviating the ramp current from id eal, can affect f cross and phase margin. lastly, set c c2 to comp c comp c c c 10 1 20 1 2 (13) switching noise and overshoot reduction in any high speed step - down regulator, high frequency noise (generally in the range of 50 mhz to 100 mhz) and voltage overshoot are always present at the gate, the switch node (sw), and the drains of the external mosfets. the high frequency noise and overshoot are caused by the parasitic capacitance, c gd , of the external mosfet as well as the parasitic inductance of the gate trace and the packages of the mosfets. when the high current is switched, electromagnetic interference (emi) is generated, which can affect the operation of the surrounding circuits. to reduce voltage ringing and noise, it is recommended to add an rc snubber bet ween swx and pgndx for high current applications , as illustrated in figure 32. in most applications, r snub is typically 2 ? to 4 ?, and c snub is typically 1.2 nf to 3 nf. r snub can be estimated by oss mosfet snub c l r 2 ? and c snub can be estimated by oss snub c c ? where : l mosfet is the total parasitic inductance of the high - side and low - side mosfets, typically 3 nh, and is package dependent. c oss is the total output capacitance of the high - side and low - side mosfets given in the mosfet data sheet. the size of the rc snubber compon ents need to be chosen correctly to handle the power dissipation. the power dissipated in r snub is r snub = v in 2 c snub f sw in most applications, a component size 0805 for r snub is sufficient . however, the use of an rc snubber reduces the overall efficie ncy , generally by an amount in the range of 0.1% to 0.5%. the rc snubber does not reduce the voltage overshoot.
data sheet adp1876 rev. a | page 23 of 24 a resistor, shown as r rise in figure 32 at the bst1 pin, helps to reduce overshoot and is generally between 2 ? and 4 ?. adding a resistor in series, typically between 2 ? and 4 ?, with the gate driver also helps to reduce overshoot. if a gate resistor is added, r rise is not needed. figure 32 . application circuit with a snubber pcb layout guideline for additional information about pcb layout, see the an - 1119 application note , printed circuit board layout guideline s for step - down regulators, optimizing for low noise design with dual channel switching controllers . typical applications circuit figure 33 . typical applications circuit v in adp1876 (channe l 1) dh1 vdl dl1 ilim1 r ilim1 sw1 bst1 pgnd1 r rise m1 m2 l v out c snub c outx r snub 10103-032 750k? en1 vin 100nf t o vin 750k ? vinldo voutldo vcco vdl agnd nc sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 en2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 adp1876 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 1 1 12 13 14 15 16 input 3v t o 5.5v 12.4k? 10pf 120pf 44.2k? 22pf 330pf 100nf 0.1f 0.1f 1f 4.7f 1f 2.1k ? l2 m4 m3 cout 22 cin2 v out2 1.8v@ 13 a v in 2.1k ? l1 m2 m1 22k ? cout 12 cout 21 22k? cout 1 1 cin1 cin v out1 5v@ 13 a v in = 10v t o 14v 20k? agnd pgnd 10k? cin1, cin2: 10f/x7r/25v/1210 2, grm32dr71e106ka12, mur at a cout 1 1 , cout 21 : 330f/6.3v/posca p 2, 6tpf330m9l, sanyo cout 12 , cout 22 : 22f/x5r/0805/6.3v 3, grm21br60j226me39, mur at a cin = 150f/20 v , os-con, 20sep150m, sanyo l1, l2: 1.2h, wurth elektronik, 744325120 m1, m3: bsc080n03ls m2, m4: bsc030n03ls 73.2k? 10k? 1f voutldo 10103-033
adp1876 data sheet rev. a | page 24 of 24 packagi ng and ordering info rmation outline dimensions figure 34 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very thin quad (cp - 32 - 11) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adp1876 acpz -r7 ? 40c to +85c 32 - lead lead frame chip scale package [lfcsp_wq] cp -32 -11 adp1876 - evalz evaluation board 1 z = rohs compliant part. compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or 3.65 3.50 sq 3.45 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10103 - 0 - 11/11(a)

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